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| White Electronic Designs WV3HG264M72EEU-D6 ADVANCED* 1GB - 2x64Mx72 DDR2 SDRAM UNBUFFERED FEATURES 240-pin, dual in-line memory module (DIMM) Fast data transfer rates: PC2-6400*, PC2-5300*, PC2-4200 and PC2-3200 Utilizes 800*, 667*, 533 and 400 MT/s DDR2 SDRAM components VCC = VCCQ = 1.8V 0.1V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture Programmable CAS# latency (CL): 3, 4, 5 and 6 On-die termination (ODT) Serial Presence Detect (SPD) with EEPROM Gold edge contacts Dual Rank RoHS compliant Package * 240 Pin DIMM: 30.00mm (1.181") TYP DESCRIPTION The WV3HG264M72EEU is a 2x64Mx74 Double Data Rate DDR2 SDRAM high density module. This memory module consists of eighteen 64Mx8 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages, mounted on a 240-pin DIMM FR4 substrate. * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: * Vendor source control options * Industrial temperature option OPERATING FREQUENCIES PC2-3200 Clock Speed CL-tRCD-tRP * Consult factory for availability PC2-4200 266MHz 4-4-4 PC2-5300* 333MHz 5-5-5 PC2-6400* 400MHz 6-6-6 200MHz 3-3-3 January 2006 Rev. 0 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PIN CONFIGURATION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS NC NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CB2 CB3 VSS VCCQ CKE0 VCC NC NC VCCQ A11 A7 VCC A5 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Symbol A4 VCCQ A2 VCC VSS VSS VCC NC VCC A10/AP BA0 VCCQ WE# CAS# VCCQ CS1# ODT1 VCCQ VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Symbol VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS CK1 CK1# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 NC VSS CB6 CB7 VSS VCCQ CKE1 VCC NC NC VCCQ A12 A9 VCC A8 A6 Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Symbol VCCQ A3 A1 VCC CK0 CK0# VCC A0 VCC BA1 VCCQ RAS# CS0# VCCQ ODT0 A13 VCC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK2 CK2# VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VCCSPD SA0 SA1 2 WV3HG264M72EEU-D6 ADVANCED PIN NAMES Pin Name A0-A13 BA0, BA1 DQ0 ~ DQ63 CB0-CB7 DQS0 ~ DQS8 DQS0# ~ DQS8# ODT0, ODT1 CK0,CK0# - CK2, CK2# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# VCC VCCQ VSS SA0 ~ SA2 SDA SCL DM(0-8) A10/AP VREF VCCSPD NC Function Address Input Bank Address Data Input/output Check Bits Data Strobe Data Strobe negative On Die Termination Clock Input Clock enable input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Voltage Supply (1.8V0.1V) I/O Power (1.8V) Ground SPD Address Serial Data I/O Serial clock Data Masks Address input/Auto precharge I/O reference supply Serial EEPROM No Connect January 2006 Rev. 0 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M72EEU-D6 ADVANCED FUNCTIONAL BLOCK DIAGRAM CS1# CS0# DQS0 DQS0# DM0 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQS4 DQS4# DM4 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 DQS1 DQS1# DM1 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQS5 DQS5# DM5 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2# DM2 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS6 DQS6# DM6 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3# DM3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS7 DQS7# DM7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 VCCSPD Serial PD SCL WP Serial PD SDA A0 A0 A1 WP A1 A2 A2 VCC/VCCQ DDR2 SDRAMs SA0 SA1 SA2 VREF DDR2 SDRAMs VSS DDR2 SDRAMs *Clock Wiring Clock Input *CK0/CK0# *CK1/CK1# *CK2/CK2# DDR2 SDRAMs 6 DDR2 SDRAMs 6 DDR2 SDRAMs 6 DDR2 SDRAMs CS0# CS1# BA0 - BA1 A0 - A13 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 CS0# : DDR2 SDRAMs CS1# : DDR2 SDRAMs BA0 - RBA1 : DDR2 SDRAMs A0 - A13 : DDR2 SDRAMs RAS# : DDR2 SDRAMs CAS# : DDR2 SDRAMs WE# : DDR2 SDRAMs CKE0 : DDR2 SDRAMs CKE1 : DDR2 SDRAMs ODT0 : DDR2 SDRAMs ODT1 : DDR2 SDRAMs *Wire per Clock Loading Table/Wiring Diagrams Notes: 1. DQ, DM, DQS, DQS# resistors: 5.1 Ohms +/- 5% 2. BAx, Ax, RAS#, CAS#, WE# resistors: 5.1 Ohms +/- 5% NOTE: All resistor values are 22 ohms unless otherwise specified. January 2006 Rev. 0 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs DC OPERATING CONDITIONS All Voltages Referenced to VSS Rating Parameter Supply Voltage I/O Supply Voltage VCCL Supply Voltage I/O Reference Voltage I/O Termination Voltage Symbol VCC VCCQ VCCL VREF VTT Min. 1.7 1.7 1.7 0.49*VCCQ VREF-0.04 Type 1.8 1.8 1.8 0.50*VCCQ VREF WV3HG264M72EEU-D6 ADVANCED Max. 1.9 1.9 1.9 0.51*VCCQ VREF+0.04 Units V V V V V Notes 1 4 4 2 3 Notes: 1. VCC and VCCQ must track each other. VCCQ must be less than or equal to VCC. 2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/- percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 4. VCCQ tracks with VCC; VCCL track with VCC. ABSOLUTE MAXIMUM RATINGS SSTL_1.8V Symbol VCC VCCQ VCCL VIN, VOUT TSTG TCASE IL Parameter Voltage on VCC pin relative to VSS Voltage on VCCQ pin relative to VSS Voltage on VCCL pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Device operating Temperature Input leakage current; Any input 0V 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CAPACITANCE TA = 25C, f = 1MHz, VCC = VCCQ = 1.8V Parameter Input Capacitance: (A0 ~ A13 , BA0 ~ BA1, RAS#, CAS#, WE#) Input Capacitance: (CKE0, CKE1), (ODT0, ODT1) Input Capacitance: (CS0#, CS1#) Input Capacitance: (CK0, CK0# ~ CK2, CK2#) Input Capacitance: (DM0 ~ DM8), (DQS0-DQS8) Symbol CIN1 CIN2 CIN3 CIN4 CIN6 (E6) CIN6 (D5) COUT1 (E6) COUT1 (D5) WV3HG264M72EEU-D6 ADVANCED Min 22 13 13 10 9 9 9 9 Max 40 22 22 16 11 12 11 12 Units pF pF pF pF pF pF pF pF Input Capacitance: (DQ0 ~ DQ63), (CB0-CB7) OPERATING TEMPERATURE CONDITION Parameter Operating Temperature Symbol TOPER Rating 0C to 85C Units C Notes 1, 2 Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2. 2. At 0 - 85C, operation temperature range, all DRAM specification will be supported. INPUT DC LOGIC LEVEL All voltages referenced to VSS Parameter Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.300 Max VREF + 0.300 VREF - 0.125 Units V V INPUT AC LOGIC LEVEL All voltages referenced to VSS Parameter AC Input High (Logic 1) Voltage AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533 AC Input Low (Logic 0) Voltage DDR2-667, DDR2-800 (TBD) Symbol VIH(AC) VIL(AC) VIL(AC) Min VREF+ 0.250 VREF - 0.250 VREF - 0.200 Max Units V V V January 2006 Rev. 0 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M72EEU-D6 ADVANCED DDR2 ICC SPECIFICATIONS AND CONDITIONS Symbol Proposed Conditions ICC0* Operating one bank active-precharge current; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS MIN(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1 806 TBD 665 837 534 792 403 792 Units mA ICC1* TBD 972 972 972 mA ICC2P** TBD 144 144 144 mA ICC2Q** TBD 630 540 540 mA ICC2N** TBD 720 540 216 630 540 216 630 540 216 mA mA mA TBD ICC3P** TBD ICC3N** Active standby current; All banks open; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRAS MAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRAS MAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING TBD 990 900 900 mA ICC4W** TBD 1332 1152 1062 mA ICC4R* TBD 1377 1197 1062 mA ICC5B** TBD 2700 2520 2520 mA ICC6* Normal TBD 144 144 144 mA ICC7* Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are switching. TBD 2052 2052 2052 mA * Value calculated as one module rank in thes operating condition, and all other module ranks in January 2006 Rev. 0 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs AC TIMING PARAMETERS WV3HG264M72EEU-D6 ADVANCED 0C TCASE < +85C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V AC CHARACTERISTICS PARAMETER CL = 6 CL = 5 CL = 4 CL = 3 SYMBOL tCK (6) tCK (5) tCK (4) tCK (3) tCH tCL tHP tAC tHZ tLZ tDS tDH tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS tDSH tDQSQ tRPRE tRPST tWPRES tWPRE tWPST tDQSS tIPW MIN TBD TBD TBD TBD TBD TBD TBD TBD TBD 806 MAX TBD TBD TBD TBD TBD TBD TBD TBD TBD 665 MIN 3000 3750 5000 0.45 0.45 MIN (tCH, tCL) -450 MAX 8000 8000 8000 0.55 0.55 MIN 534 MAX MIN 403 MAX UNIT ps ps ps ps tCK tCK ps +600 tAC (MAX) tAC (MIN) 150 275 0.35 400 450 tHP - tQHS tQH - tDQSQ 0.35 0.35 -500 0.2 0.2 tAC (MAX) ps ps ps ps ps tCK ps ps ns tCK tCK ps tCK tCK ps tCK tCK ps tCK tCK tCK tCK Continued on next page Clock cycle time Clock 3,750 5,000 0.45 0.45 MIN (tCH, tCL) -500 8,000 8,000 0.55 0.55 5,000 5,000 0.45 0.45 MIN (tCH, tCL) -600 8,000 8,000 0.55 0.55 CK high-level width CK low-level width Half clock period DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS A DQ and DM input pulse width (for each input) Data hold skew factor DQ...DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# DQS falling edge to CK rising ... setup time DQS falling edge from CK rising ... hold time DQS...DQ skew, DQS to last DQ valid, per group, per access DQS read preamble DQS read postamble DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition Address and control input pulse width for each input +450 tAC (MAX) +500 tAC (MAX) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD tAC (MIN) 100 225 0.35 tAC (MAX) tAC (MIN) 100 225 0.35 tAC (MAX) Data 340 tHP - tQHS tQH - tDQSQ 0.35 0.35 -400 0.2 0.2 tHP - tQHS tQH - tDQSQ 0.35 0.35 -450 0.2 0.2 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD +400 +450 +500 Data Strobe TBD TBD 240 0.9 0.4 0 0.35 0.4 WL - 0.25 0.6 1.1 0.6 0.9 0.4 0 0.35 0.4 WL - 0.25 0.6 300 1.1 0.6 0.9 0.4 0 0.35 0.4 WL - 0.25 0.6 350 1.1 0.6 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 0.6 WL + 0.25 0.6 WL + 0.25 0.6 WL + 0.25 TBD TBD NOTE: * AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. January 2006 Rev. 0 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M72EEU-D6 ADVANCED AC TIMING PARAMETERS (cont'd) 0C TCASE < +85C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V AC CHARACTERISTICS PARAMETER SYMBOL Address and control input setup time tIS Address and control input hold time tIH CAS# to CAS# command delay tCCD ACTIVE to ACTIVE (same bank) command tRC ACTIVE bank a to ACTIVE bank b command tRRD ACTIVE to READ or WRITE delay tRCD Four Bank Activate period tFAW ACTIVE to PRECHARGE command tRAS Internal READ to precharge command delay tRTP Write recovery time tWR Auto precharge write recovery + precharge time tDAL Internal WRITE to READ command delay tWTR PRECHARGE command period tRP PRECHARGE ALL command period tRPA LOAD MODE command cycle time tMRD CKE low to CK,CK# uncertainty tDELAY REFRESH to REFRESH command interval Average periodic refresh interval Exit self refresh to non-READ command Exit self refresh to READ command Exit self refresh timing reference ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off ODT ODT turn-on (power-down mode) tRFC tREFI tXSNR tXSRD tISXR tAOND tAON tAOFD tAOF tAONPD MIN TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 806 MAX TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 665 534 403 MIN MAX MIN MAX MIN MAX UNIT 200 250 250 ps 275 375 475 ps 2 2 2 tCK 55 55 55 ns 7.5 7.5 7.5 ns 15 15 15 ns 37.5 37.5 37.5 37.5 37.5 37.5 45 70,000 45 70,000 45 70,000 ns 7.5 7.5 7.5 ns 15 15 15 ns tWR + tRP tWR + tRP tWR + tRP ns 10 7.5 10 ns 15 15 15 tWR + tCK tWR + tCK tWR + tCK ns 2 2 2 tCK tIS + tCK + tIH tIS + tCK + tIH tIS + tCK + tIH ns 127.5 70,000 7.8 tRFC (MIN) + 10 200 tIS 2 tRFC (MIN) + 10 200 tIS 2 127.5 70,000 7.8 tRFC (MIN) + 10 200 tIS 2 127.5 70,000 7.8 ns s ns tCK ps tCK Self Refresh Refresh Command and Address 2 2 2 tAC (MAX) tAC (MAX) tAC (MAX) tAC (MIN) tAC (MIN) ps tAC (MIN) + 1000 + 1000 + 1000 2.5 2.5 tAC (MAX) tAC (MIN) tAC (MIN) + 600 2 x tCK + tAC (MIN) + tAC (MIN) + tAC (MAX) 2000 2000 + 1000 2.5 x tCK + tAC (MIN) + tAC (MIN) + tAC (MAX) 2000 2000 + 1000 3 3 8 8 2 2 7-AL 2 3 6 - AL 2 3 2.5 2.5 2.5 tAC (MAX) tAC (MIN) + 600 2 x tCK + tAC (MIN) + tAC (MAX) 2000 + 1000 2.5 x tCK + tAC (MIN) + tAC (MAX) 2000 + 1000 3 8 2 6 - AL 2 3 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000 tCK ps ps TBD TBD ODT turn-off (power-down mode) ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] A Exit precharge power-down to any non-READ command. CKE minimum high/low time tAOFPD tANPD tAXPD tXARD tXARDS tXP tCKE TBD TBD ps tCK tCK tCK tCK tCK tCK TBD TBD TBD TBD TBD TBD Power-Down TBD TBD TBD TBD TBD TBD NOTE: * AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. January 2006 Rev. 0 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M72EEU-D6 ADVANCED ORDERING INFORMATION FOR D6 Part Number W3HG264M72EEU806D6xG** W3HG264M72EEU665D6xG** W3HG264M72EEU534D6xG W3HG264M72EEU403D6xG Clock/Data Rate Frequency 400MHz/800Mb/s 333MHz/667Mb/s 266MHz/533Mb/s 200MHz/400Mb/s CAS Latency 6 5 4 3 tRCD 6 5 4 3 tRP 6 5 4 3 Height* 30.00mm (1.181") TYP 30.00mm (1.181") TYP 30.00mm (1.181") TYP 30.00mm (1.181") TYP ** Consult factory for availability NOTES: * RoHS compliant product. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options. (G = Infineon, M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option PACKAGE DIMENSIONS FOR D6 FRONT VIEW 133.35 (5.25) 133.20 (5.244) 3.00 (0.118) (4x) + + 4.00 (0.158) (4x) PIN 1 1.50 0.10 (0.059 0.004) 5.00 (0.196) 10.00 (0.394) TYP 4.00 (0.158) 0.80 0.05 (0.032 0.002) TYP PIN 20 1.00 (0.039) TYP 30.50 (1.201) 29.85 (1.175) 17.80 (0.700) TYP 2.50 0.20 (0.098 0.007) 0.158 (4.00) MAX BACK VIEW 63.00 (2.48) TYP 55.00 (2.165) TYP PIN 121 PIN 1 0.054 (1.37) 0.046 (1.17) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) January 2006 Rev. 0 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M72EEU-D6 ADVANCED PART NUMBERING GUIDE WV 3 H G 2 64M 72 E E U xxx D6 x G WEDC MEMORY (SDRAM) DDR 2 GOLD DUAL RANK DEPTH BUS WIDTH COMPONENT WIDTH x8 1.8V UNBUFFERED SPEED (Mb/s) PACKAGE 240 PIN COMPONENT VENDOR NAME (G = Infineon) (M = Micron) (S = Samsung) G = RoHS COMPLIANT January 2006 Rev. 0 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title 1GB - 2x64Mx72 DDR2 SDRAM UNBUFFERED WV3HG264M72EEU-D6 ADVANCED Revision History Rev # Rev 0 History Created Release Date January 2006 Status Advanced January 2006 Rev. 0 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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